1. Field of the Invention
The present invention generally relates to yield estimation techniques for large complex circuit designs and, more particularly, to an incremental method for critical area computation of via blocks in very large scale integrated (VLSI) circuits.
2. Background Description
Very large scale integrated (VLSI) circuit yield prediction is based on the concept of critical area which reflects the sensitivity of the chip to defects occurring during the manufacturing process. A via block is a missing material defect that overlaps with a via and thus destroys its connectivity. Via blocks occur frequently during fabrication and thus computing the critical area fast is an important problem in yield prediction.